1. Field of the Invention
The present invention relates to an adiabatic charging register circuit and, in particular, relates to such a circuit which reduces power consumption associated with a clock pulse.
2. Description of the Related Art
Conventionally, an LSI circuit includes a large number of register circuits, fifty thousand or more circuits. Each register circuit comprises a D-flip flop (D-FF) or D-latch circuit. A register circuit having a D-FF or D-latch is exemplified here.
First, a register circuit having a D-FF is described.
A D-FF has a pair of D-latch circuits. FIG. 17 shows an example of a D-latch circuit (page 677, “Structure and Design of a Computer”, by David A. Patterson and John L. Hennessy, published by NikkeiBP). A D-latch circuit 70 in FIG. 17 has a pair of NOR circuits 71 and 72 which are cross-connected to each other constituting a RS-FF (reset-set-flip-flop), and a pair of AND circuits 73 and 74. It has data input terminals D, DN in differential form, a clock input terminal CK, and data output terminals Q, QN in differential form. Each of NOR circuits 71 and 72 operates as an inverter when one of the inputs of the same is in low state, and therefore, a D-latch circuit 70 in FIG. 17 operates as follows.
(1) A pair of NOR circuits 71, 72 keep a previous state when a clock input terminal CK is in low state.
(2) A value of a data input terminal D is stored in a pair of NOR circuits 71, 72 when a clock input terminal CK is in high state.
A D-FF circuit 80 is constituted by using a pair of D-latch circuits 70 as shown in FIG. 18, in which a first stage D-latch circuit 70A receives a clock input CK as it is, and a second stage D-latch circuit 70B receives a clock signal which is inversion by 180° of the clock input CK by an inverter 90. A D-FF circuit operates as follows.
(1) When a clock input CK becomes a high state, the first stage D-latch circuit 70A opens to accept a data D at an input terminal,
(2) When a clock input CK becomes a low state, the second stage D-latch circuit 70B opens and an input terminal D accepts an output O1 on an output terminal Q of the first stage D-latch 70A, as an input signal D.
FIG. 19 shows operational wave forms of a data D, a clock input CK, an output O1 of the first stage D-latch circuit 70A, and an output O2 of the second stage D-latch circuit 70B. As shown in FIG. 19, the output O2 is switched by an input data when a clock input CK is switched from high state to low state, thus, it is an edge trigger type circuit.
Conventionally, a clock signal CK is generated by using an inverter having a CMOS circuit which has a p-channel MOSFET and an n-channel MOSFET connected in series with each other, and has rectangular wave form. A load coupled with an output of a clock signal generator is charged to power supply voltage VDD through p-channel MOSFET of an inverter when an output signal is in high state, and is discharged to ground through n-channel MOSFET of an inverter when an output signal is in a low state. Therefore, the power consumption P by a clock signal is P=CV2f, where f is the clock frequency, V is the power supply voltage, and C is the sum of capacitance of wires and gate capacitance which accept a clock signal.
The capacitance of wires is recently large because of an increase of semiconductor chip area of an integrated circuit reflecting a large scale integrated circuit, and therefore, power consumption by charge/discharge of a clock signal occupies almost 50% of the total power consumption of a semiconductor chip (page 90, Technical Report of Low Power LSI, Nikkei Micro-device, NikkeiBP).
Further, a large number of register circuits are used for a pipeline processing in an LSI for processing a moving image, and a RISC processor. In those devices, it is also known that power consumption by a clock system is almost the same as that by a logic system (page 8, Low power and high speed LSI technology, Realize Co.). That relation is independent from operation speed, but depends upon the ratio occupied by a register circuit in an LSI.